US 11,837,569 B2
Semiconductor device and manufacturing method thereof
Yoshiharu Okada, Yokkaichi (JP); Masatoshi Kawato, Kameyama (JP); and Keiichi Niwa, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 18, 2021, as Appl. No. 17/178,434.
Claims priority of application No. 2020-138900 (JP), filed on Aug. 19, 2020.
Prior Publication US 2022/0059493 A1, Feb. 24, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/18 (2023.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 24/32 (2013.01) [H01L 23/3135 (2013.01); H01L 24/33 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/3207 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32238 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/83193 (2013.01); H01L 2224/92247 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer;
a first semiconductor chip electrically connected to a first electrode of the electrodes having a top surface higher than a top of the second resin layer;
a second semiconductor chip provided above the first semiconductor chip, being larger than the first semiconductor chip, and connected to a second electrode of the electrodes via a metal wire; and
a third resin layer provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, contacting the top surface of the first semiconductor chip and the top surface of the second resin layer, and covering the first semiconductor chip, the second resin layer extending beyond the third resin layer, wherein
the first semiconductor chip includes a bottom surface opposing the first surface and is electrically connected to the first electrode via a third electrode provided on the bottom surface.