US 11,837,551 B2
Semiconductor package
Jongyoun Kim, Seoul (KR); Seokhyun Lee, Hwaseong-si (KR); and Gwangjae Jeon, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 29, 2021, as Appl. No. 17/215,517.
Claims priority of application No. 10-2020-0115325 (KR), filed on Sep. 9, 2020.
Prior Publication US 2022/0077066 A1, Mar. 10, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 23/5386 (2013.01); H01L 24/14 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a semiconductor chip;
a connection terminal; and
a redistribution substrate configured to electrically connect to the semiconductor chip via the connection terminal, the redistribution substrate including,
a pad pattern including a pad via and a pad on the pad via,
a first redistribution pattern including a first via and a first interconnection on the first via, and
a second redistribution pattern between the first redistribution pattern and the pad pattern, the second redistribution pattern including a second via and a second interconnection on the second via, the second interconnection having a recess region therein where a portion of a top surface of the second interconnection is recessed with a bottom surface of the recess region located at a lower level than a topmost surface of the second interconnection, the pad via filling a portion of the recess region such that a bottom surface of the pad via is higher than a bottom surface of the second interconnection in a direction perpendicular to the top surface of the second interconnection.