US 11,837,548 B2
Semiconductor device and method for fabricating the same
Seon Bae Kim, Hwaseong-si (KR); and Seo Woo Nam, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 16, 2021, as Appl. No. 17/476,985.
Claims priority of application No. 10-2021-0020867 (KR), filed on Feb. 17, 2021.
Prior Publication US 2022/0262739 A1, Aug. 18, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/3213 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/53295 (2013.01) [H01L 21/3213 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first interlayer insulating layer disposed on the substrate;
a first trench formed inside the first interlayer insulating layer;
a contact plug disposed inside the first trench;
a first wiring pattern disposed inside the first trench on the contact plug;
a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction;
a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern; and
a first air gap formed on the contact plug inside the first trench.
 
13. A semiconductor device comprising:
a substrate;
a first interlayer insulating layer disposed on the substrate;
a first trench formed inside the first interlayer insulating layer;
a contact plug disposed inside the first trench;
a first wiring pattern disposed inside the first trench on the contact plug;
a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction;
a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern; and
a first air gap and a second air gap which are formed on the contact plug inside the first trench, and spaced apart from each other in the horizontal direction,
wherein a height from an upper surface of the contact plug to an upper surface of the first interlayer insulating layer is greater than a pitch between the first trench and the second wiring pattern in the horizontal direction, and
a width of the first wiring pattern in the horizontal direction increases toward the contact plug.
 
17. A method for fabricating a semiconductor device, the method comprising:
forming a first interlayer insulating layer including a trench, on a substrate;
forming a contact plug inside the trench;
forming a first wiring pattern inside the trench on the contact plug;
forming a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction;
forming a second interlayer insulating layer which surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern on the first interlayer insulating layer;
forming an air gap between the contact plug and the second interlayer insulating layer inside the trench in a vertical direction; and
forming a third interlayer insulating layer on the second interlayer insulating layer,
wherein an upper surface of the air gap is formed lower than an upper surface of the first interlayer insulating layer.