US 11,837,545 B2
Semiconductor memory device
Jungwoo Song, Hwaseong-si (KR); Ye-Ro Lee, Seoul (KR); Kwangtae Hwang, Seoul (KR); Kwangmin Kim, Hwaseong-si (KR); Yong Kwan Kim, Yongin-si (KR); and Jiyoung Kim, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 10, 2021, as Appl. No. 17/399,043.
Application 17/399,043 is a division of application No. 16/561,008, filed on Sep. 4, 2019, abandoned.
Application 16/561,008 is a continuation of application No. 15/706,655, filed on Sep. 15, 2017, granted, now 10,453,796, issued on Oct. 22, 2019.
Claims priority of application No. 10-2016-0173827 (KR), filed on Dec. 19, 2016.
Prior Publication US 2021/0375764 A1, Dec. 2, 2021
Int. Cl. H10B 12/00 (2023.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5329 (2013.01) [H01L 21/768 (2013.01); H01L 27/0207 (2013.01); H10B 12/033 (2023.02); H10B 12/053 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H01L 21/7682 (2013.01); H01L 21/76897 (2013.01); H01L 23/5222 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
a device isolation layer disposed in the substrate defining an active region extending in a first direction;
first conductive lines disposed in the active region and extending in a second direction crossing the first direction;
a second conductive line disposed on the active region between the first conductive lines and extending in a third direction crossing the first direction and the second direction;
an insulating pattern disposed on the second conductive line;
a bit line node contact disposed between the active region and the second conductive line;
a landing pad disposed on an edge portion of the active region;
a storage node contact between the landing pad and the edge portion of the active region;
a buried pattern disposed between the bit line node contact and the storage node contact;
a first spacer disposed between a sidewall of the second conductive line and the landing pad;
an air spacer disposed between the first spacer and the landing pad; and
a capping pattern protruding from a sidewall of the landing pad and disposed on the air spacer,
wherein the capping pattern is spaced apart from the first spacer, and
wherein the air spacer is in contact with a sidewall of the insulating pattern.