US 11,837,512 B2
Resistance patterns for an On-Die EPM
Oh Kyu Kwon, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 31, 2021, as Appl. No. 17/462,118.
Claims priority of application No. 10-2021-0034733 (KR), filed on Mar. 17, 2021.
Prior Publication US 2022/0301953 A1, Sep. 22, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 23/522 (2006.01)
CPC H01L 22/34 (2013.01) [H01L 22/32 (2013.01); H01L 23/5226 (2013.01); H01L 23/5228 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first resistance chain including first upper resistance segments, first resistance via plugs, and first lower resistance segments;
a second resistance chain including second upper resistance segments, second resistance via plugs, and second lower resistance segments; and
a third resistance chain including third upper resistance segments, third resistance via plugs, and third lower resistance segments,
wherein:
each of the first upper resistance segments has a first upper effective resistance distance,
each of the second upper resistance segments has a second upper effective resistance distance,
each of the third upper resistance segments has a third upper effective resistance distance,
the first upper effective resistance distance is equal to the third upper effective resistance distance, and
the second upper effective resistance distance is an N times greater than the first upper effective resistance distance, where the N is a positive integer greater than one.