US 11,837,502 B2
Semiconductor package and methods of forming the same
Meng-Che Tu, Hsinchu (TW); Wei-Chih Chen, Taipei (TW); Sih-Hao Liao, New Taipei (TW); Yu-Hsiang Hu, Hsinchu (TW); Hung-Jui Kuo, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 7, 2021, as Appl. No. 17/341,015.
Application 17/341,015 is a division of application No. 16/399,710, filed on Apr. 30, 2019, granted, now 11,031,289.
Claims priority of provisional application 62/753,527, filed on Oct. 31, 2018.
Prior Publication US 2021/0296270 A1, Sep. 23, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 21/82 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01)
CPC H01L 21/82 (2013.01) [H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 24/08 (2013.01); H01L 24/17 (2013.01); H01L 2224/02372 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a die having a die connector and a passivation layer, wherein the die connector extends through the passivation layer;
a first dielectric layer over the passivation layer and around the die connector, wherein the first dielectric layer extends along sidewalls of the die connector, wherein the first dielectric layer has a first portion in contact with the die connector and has a second portion spaced apart from the die connector, wherein an upper surface of the first portion of the first dielectric layer distal from the passivation layer extends further from the passivation layer than an upper surface of the second portion of the first dielectric layer distal from the passivation layer; and
a molding material around the die and the first dielectric layer.