US 11,837,458 B2
Substrate with gradiated dielectric for reducing impedance mismatch
Jackson Chung Peng Kong, Tanjung Tokong (MY); Bok Eng Cheah, Bukit Gambir (MY); Ping Ping Ooi, Butterworth (MY); and Kooi Chi Ooi, Glugor (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 11, 2021, as Appl. No. 17/498,089.
Application 17/498,089 is a continuation of application No. 16/473,962, granted, now 11,164,827, previously published as PCT/US2017/067366, filed on Dec. 19, 2017.
Claims priority of application No. 2016704903 (MY), filed on Dec. 30, 2016.
Prior Publication US 2022/0102295 A1, Mar. 31, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/66 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 21/481 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 2223/6616 (2013.01); H05K 3/0094 (2013.01); H05K 3/426 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
a substrate having a first side and a second side, the substrate including a first dielectric characteristic, the substrate further including a hole transverse to the first side, the hole extending from the first side to the second side;
a material disposed within the hole, the material including a second dielectric characteristic, wherein the second dielectric characteristic is different than the first dielectric characteristic;
a first conductive layer disposed on the first side and a second conductive layer disposed on the second side; and
a conductive path electrically coupled between the first conductive layer and the second conductive layer, wherein the conductive path is in contact with at least a portion of the material and traverses through the hole.