CPC G11C 7/222 (2013.01) [G11C 7/109 (2013.01); G11C 7/1045 (2013.01); G11C 7/1063 (2013.01); G11C 8/18 (2013.01)] | 9 Claims |
1. An apparatus comprising:
a plurality of signal pins respectively connected to an external device through a plurality of signal lines; and
a clock control circuit configured to instruct the external device through some of the plurality of signal pins to perform one operation having a first operation mode and a second operation mode, and configured to generate a clock signal relating to the first operation mode and the second operation mode for the one operation of the external device,
wherein the clock control circuit is configured to switch a frequency of the clock signal to a first frequency during the first operation mode of the one operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during the second operation mode according to de-assertion of a status signal of the external device provided to the apparatus from the external device, and
wherein the external device comprises a nonvolatile memory device, and
wherein the one operation is a read operation of the nonvolatile memory device, and
the clock control circuit is configured to generate the clock signal having a low frequency while the nonvolatile memory device reads data stored in a memory cell of the nonvolatile memory device, and generate the clock signal having a high frequency while the nonvolatile memory device transmits the data read from the nonvolatile memory device to the apparatus.
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