US 11,837,310 B2
Memory device for correcting pulse duty and memory system including the same
Jaehyeong Hong, Gyeonggi-do (KR); In Seok Kong, Gyeonggi-do (KR); Gwan Woo Kim, Gyeonggi-do (KR); Jae Young Park, Gyeonggi-do (KR); Kwan Su Shon, Gyeonggi-do (KR); Soon Sung An, Gyeonggi-do (KR); Daeho Yang, Gyeonggi-do (KR); Sung Hwa Ok, Gyeonggi-do (KR); Junseo Jang, Gyeonggi-do (KR); Yo Han Jeong, Gyeonggi-do (KR); and Eun Ji Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 5, 2022, as Appl. No. 17/569,144.
Claims priority of application No. 10-2021-0110373 (KR), filed on Aug. 20, 2021.
Prior Publication US 2023/0056686 A1, Feb. 23, 2023
Int. Cl. G11C 29/44 (2006.01); G11C 29/12 (2006.01); H03K 5/15 (2006.01); H03K 19/17736 (2020.01); H03K 5/156 (2006.01); H03K 19/20 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/12015 (2013.01); H03K 5/1565 (2013.01); H03K 5/15066 (2013.01); H03K 19/1774 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device including a plurality of memory blocks and a primary pulse correction module; and
a controller configured to transmit a control signal for controlling the memory device,
wherein the primary pulse correction module includes:
a reset signal generation circuit configured to generate a reset signal on the basis of the control signal;
a primary pulse detection circuit configured to output a detection signal by detecting a primary pulse of the control signal on the basis of the reset signal; and
a corrected primary pulse output circuit configured to correct a duty ratio of the primary pulse of the control signal to be outputted by adjusting a rising edge of the detection signal after the end of a preamble period of the control signal.