US 11,837,293 B2
Memory device including pass transistor circuit
Seungyeon Kim, Seoul (KR); Daeseok Byeon, Seongnam-si (KR); Pansuk Kwak, Goyang-si (KR); and Hongsoo Jeon, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 30, 2022, as Appl. No. 17/898,885.
Application 17/898,885 is a continuation of application No. 17/227,501, filed on Apr. 12, 2021, granted, now 11,462,275.
Claims priority of application No. 10-2020-0134611 (KR), filed on Oct. 16, 2020.
Prior Publication US 2022/0406385 A1, Dec. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/00 (2006.01); G11C 16/24 (2006.01); G11C 5/06 (2006.01); G11C 16/26 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC G11C 16/24 (2013.01) [G11C 5/06 (2013.01); G11C 16/26 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction;
driving signal lines respectively corresponding to vertically stacked word lines;
a first pass transistor circuit connected between the driving signal lines and the first memory block, the first pass transistor circuit including a first plurality of pass transistors controlled by a first block selection signal corresponding to the first memory block; and
a second pass transistor circuit connected between the driving signal lines and the second memory block, the second pass transistor circuit including a second plurality of pass transistors controlled by a second block selection signal corresponding to the second memory block,
wherein the first plurality of pass transistors and the second plurality of pass transistors are divided into an odd number of pass transistor groups disposed in the first direction,
wherein one of the odd number of pass transistor groups includes:
a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and
a second pass transistor connected between a first word line of the second memory block and the first driving signal line, wherein the second pass transistor is adjacently disposed to the first pass transistor in a second direction.