US 11,837,285 B2
Bias temperature instability correction in memory arrays
Christophe J. Chevallier, Palo Alto, CA (US); and Siddarth Krishnan, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Aug. 22, 2021, as Appl. No. 17/408,429.
Prior Publication US 2023/0058423 A1, Feb. 23, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01)
CPC G11C 13/0023 (2013.01) [G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 13/0069 (2013.01); G11C 2213/79 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of correcting bias temperature instability in memory arrays, the method comprising:
applying a first bias to a first memory cell in a memory array, wherein the first bias is applied as part of an operation to store a value in a second memory cell in a memory array, wherein the first bias comprises a SET signal, a RESET signal, and/or a signal for one of a plurality of intermediate memory states between a SET state and a RESET state; and
applying a second bias to the first memory cell, wherein:
the second bias comprises a polarity that is opposite of the first bias; and
any value stored in the first memory cell remains in the first memory cell after the second bias is applied.