US 11,837,284 B2
Nonvolatile semiconductor memory device
Masanobu Shirakawa, Chigasaki (JP); and Takayuki Akamine, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 17, 2022, as Appl. No. 18/056,587.
Application 18/056,587 is a continuation of application No. 17/343,426, filed on Jun. 9, 2021, granted, now 11,557,339.
Application 17/343,426 is a continuation of application No. 16/783,575, filed on Feb. 6, 2020, granted, now 11,069,403, issued on Jul. 20, 2021.
Application 16/783,575 is a continuation of application No. 15/459,542, filed on Mar. 15, 2017, granted, now 10,593,398, issued on Mar. 17, 2020.
Claims priority of provisional application 62/393,744, filed on Sep. 13, 2016.
Prior Publication US 2023/0081358 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/10 (2006.01); G06F 11/10 (2006.01); H03M 13/29 (2006.01); H03M 13/00 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01)
CPC G11C 11/5642 (2013.01) [G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/3459 (2013.01); G11C 29/52 (2013.01); H03M 13/2906 (2013.01); G11C 2029/0411 (2013.01); G11C 2211/5642 (2013.01); G11C 2211/5643 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device comprising:
first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, each of the plurality of memory cells being capable of storing four bit data, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell and a second memory cell;
a bit line electrically connected to the first and the second strings;
a first select gate line electrically connected to a gate of the select transistor of the first string;
a second select gate line electrically connected to a gate of the select transistor of the second string;
a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string;
a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string; and
a control unit configured to perform a first write operation and a second write operation to each of the first memory cell and the second memory cell to write data to each of the first memory cell and the second memory cell, wherein
the control unit is configured to
perform the first write operation to the first memory cell of the first string,
perform the first write operation to the first memory cell of the second string after performing the first write operation to the first memory cell of the first string,
perform the first write operation to the second memory cell of the first string after performing the first write operation to the first memory cell of the second string,
perform the second write operation to the first memory cell of the first string after performing the first write operation to the second memory cell of the first string, and
perform the second write operation to the first memory cell of the second string after performing the second write operation to the first memory cell of the first string.