US 11,837,167 B2
Display device optimizing power control signal of source driver integrated circuit to optimize power consumption
MinKi Kim, Daegu (KR); JinSung Kim, Seoul (KR); and JinCheol Hong, Paju-si (KR)
Assigned to LG DISPLAY CO., LTD., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on Jun. 30, 2022, as Appl. No. 17/854,776.
Claims priority of application No. 10-2021-0086039 (KR), filed on Jun. 30, 2021.
Prior Publication US 2023/0005425 A1, Jan. 5, 2023
Int. Cl. G09G 3/3233 (2016.01); G09G 3/20 (2006.01); G09G 3/3283 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/2074 (2013.01); G09G 3/3283 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2360/10 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display device, comprising:
a display panel including a plurality of sub pixels configured to emit light having different colors;
a data driver configured to output a data voltage to the plurality of sub pixels via a plurality of data lines; and
a timing controller configured to output a plurality of power control signals for controlling a driving current which drives the data driver,
wherein the plurality of data lines includes a plurality of first data lines, a plurality of second data lines, a plurality of third data lines, and a plurality of fourth data lines,
each of the plurality of first data lines, each of the plurality of second data lines, each of the plurality of third data lines, and each of the plurality of fourth data lines are sequentially disposed,
the data driver includes a plurality of source driving integrated circuits connected to the plurality of data lines to output the data voltage to each of the plurality of data lines,
each of the plurality of source driving integrated circuits includes:
a plurality of power control circuits configured to generate the driving current in accordance with each of the plurality of power control signals; and
a plurality of amplifiers configured to be applied with the driving current to output the data voltage to each of the plurality of data lines, and
among the plurality of amplifiers, at least one amplifier connected to any one of the plurality of first data lines, the plurality of second data lines, the plurality of third data lines, and the plurality of fourth data lines is connected to a same power control circuit among the plurality of power control circuits to be applied with a same power control signal,
wherein the same power control circuit is configured to control an amplification ratio of each of the plurality of amplifiers to control power consumption of each of the plurality of amplifiers, and
wherein the timing controller includes:
a data enable signal generator configured to generate a sub data enable signal which determines a timing to output the data voltage to the plurality of sub pixels;
a data delaying unit configured to delay a video data by one horizontal period to output delayed video data;
a data comparator configured to compare the video data and the delayed video data to generate comparison data; and
a power control signal generator configured to generate the power control signal using the comparison data.