CPC G06F 7/5443 (2013.01) [G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06G 7/16 (2013.01); G06N 3/063 (2013.01)] | 20 Claims |
1. A neural network device comprising:
a shift register circuit comprising registers configured to, in each cycle of plural cycles, transfer stored data to a next register and store new data received from a previous register;
a control circuit configured to sequentially input data of input activations included in an input feature map into the shift register circuit in a preset order; and
a processing circuit, comprising crossbar array groups that receive the input activations from at least one of the registers and perform a multiply-accumulate (MAC) operation with respect to the received input activation and weights, configured to select at least some of operation results output from the crossbar array groups at a preset number of cycles to be converted and accumulate and add the at least some operation results using a result of the converted to obtain an output activation in an output feature map.
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