US 11,836,435 B1
Machine learning based parasitic estimation for an integrated circuit chip design
Seungil Kang, Mountain View, CA (US); Koohak Kim, Mountain View, CA (US); and Prasanna Srinivas, Mountain View, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Aug. 5, 2021, as Appl. No. 17/395,355.
Claims priority of provisional application 63/063,101, filed on Aug. 7, 2020.
Int. Cl. G06F 30/398 (2020.01); G06N 20/00 (2019.01); G06F 30/394 (2020.01); G06F 119/02 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/394 (2020.01); G06N 20/00 (2019.01); G06F 2119/02 (2020.01)] 18 Claims
OG exemplary drawing
 
1. A method for parasitic analysis, comprising:
determining, by one or more processors, one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, wherein the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of the design, wherein the density map includes a density value generated for each of multiple cells of the design and each of multiple layers associated with the design;
estimating parasitic information associated with the design based on the one or more output features including the density map; and
outputting the parasitic information.