US 11,836,262 B2
Protection of communications between trusted execution environment and hardware accelerator utilizing enhanced end-to-end encryption and inter-context security
Salessawi Ferede Yitbarek, Hillsboro, OR (US); Lawrence A. Booth, Jr., Phoenix, AZ (US); Brent D. Thomas, Chandler, AZ (US); Reshma Lal, Portland, OR (US); Pradeep M. Pappachan, Tualatin, OR (US); and Akshay Kadam, Bangalore (IN)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 3, 2022, as Appl. No. 17/958,621.
Application 17/958,621 is a continuation of application No. 16/774,719, filed on Jan. 28, 2020, granted, now 11,461,483.
Prior Publication US 2023/0026602 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/00 (2013.01); G06F 21/60 (2013.01); G06F 21/76 (2013.01); H04L 9/08 (2006.01); H04L 9/14 (2006.01)
CPC G06F 21/606 (2013.01) [G06F 21/76 (2013.01); H04L 9/0827 (2013.01); H04L 9/14 (2013.01); G06F 2221/2149 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processors having one or more trusted execution environments (TEEs) including a first TEE, the first TEE to include a first trusted application;
an interface with a hardware accelerator, the hardware accelerator including authenticated software or firmware; and
a computer memory, the computer memory to store a kernel mode driver for the hardware accelerator;
wherein the one or more processors are to:
establish a secure channel between the first trusted application in the first TEE and the authenticated software or firmware of the hardware accelerator,
generate a first data from the first trusted application,
generate an integrity tag for the first data, and
transfer the first data and the integrity tag to the hardware accelerator.