US 11,836,082 B2
Neural processing device and load/store method of neural processing device
Jinwook Oh, Seongnam-si (KR); Jinseok Kim, Seongnam-si (KR); Donghan Kim, Seongnam-si (KR); and Kyeongryeol Bong, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Oct. 4, 2022, as Appl. No. 17/938,024.
Claims priority of application No. 10-2021-0149224 (KR), filed on Nov. 2, 2021.
Prior Publication US 2023/0140309 A1, May 4, 2023
Int. Cl. G06F 12/0875 (2016.01); G06F 9/30 (2018.01); G06N 3/04 (2023.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01)
CPC G06F 12/0875 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/383 (2013.01); G06F 15/8023 (2013.01); G06N 3/04 (2013.01); G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural processing device comprising:
a processing unit configured to receive an input activation and a weight and perform a two-dimensional matrix calculation with the input activation and the weight to generate an output activation;
a first memory; and
a load-store unit (LSU) configured to perform memory access operations between the first memory and a second memory,
wherein the memory access operations include a main memory access operation for a current processing operation that is performed by the processing unit, and a standby memory access operation for a standby processing operation that is performed by the processing unit after the current processing operation,
wherein a level of the first memory is equal to a level of the processing unit, and a level of the second memory is different from the level of the first memory, and
wherein the LSU comprises:
a main LSU configured to perform the main memory access operation between the first memory and the second memory; and
a hidden LSU configured to perform the standby memory access operation between the first memory and the second memory.