US 11,836,039 B2
Memory controller and memory system
Yoshiki Saito, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Sep. 3, 2021, as Appl. No. 17/466,183.
Claims priority of application No. 2021-0458592 (JP), filed on Mar. 23, 2021.
Prior Publication US 2022/0308953 A1, Sep. 29, 2022
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/0793 (2013.01) [G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/1004 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory controller for controlling a plurality of non-volatile memory chips, the memory controller comprising:
a memory configured to store first data; and
a processing unit configured to:
during a write operation, generate second data including the first data and additional data corresponding to the first data, change a bit order of the second data based on information indicating a state of a write destination for the second data, write the second data having the changed bit order to a plurality of non-volatile memory chips, and
during a read operation, read the second data having the changed bit order from the plurality of non-volatile memory chips and then restore the bit order of the second data to an original state based on the information indicating the state of the write destination of the second data, wherein
the information indicating the state of the write destination of the second data includes at least one of:
a number of readings from the write destination,
a frequency of writings to the write destination,
a frequency of readings from the write destination, and
a frequency of erasings of the write destination, and
the processing unit is configured to:
during a write operation, make a first determination to determine whether to change the bit order of the second data based on a type of the first data, then perform a first change process for changing the bit order of the second data when the first determination is that the bit order is to be changed, and not perform the first change process when the first determination is that the bit order is not to be changed, and
during a read operation, make a second determination to determine whether to restore the bit order of the second data to an original state based on the type of the first data, then perform a second change process for restoring the bit order of the second data to the original state when the second determination is that the bit order is to be restored to the original state, and not perform the second change process when the second determination is that the bit order is to be restored to the original state.