CPC G06F 1/28 (2013.01) [G06F 30/20 (2020.01); G06F 30/3308 (2020.01); G06F 2119/06 (2020.01)] | 7 Claims |
1. A method of updating a register transfer level (RTL) power model for power consumption analysis of a semiconductor circuit by at least one processor, the method comprising:
receiving a test scenario including a plurality of time slots, each of which is related to one power state;
inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots;
determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots through a gate-level simulation of the semiconductor circuit; and
updating the initial power model on the basis of the specific power state and the determined power value,
wherein the inputting of the test scenario to the initial power model and the identifying of the first set of time slots related to the power state which is not defined by the initial power model among the plurality of time slots comprises:
identifying a specific time slot section including a predetermined ratio of time slots or more related to the power state not defined by the initial power model among the plurality of time slots; and
identifying the time slots related to the power state not defined by the initial power model among time slots in the specific time slot section as the first set of time slots.
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