CPC G06F 13/4004 (2013.01) [G06F 13/364 (2013.01); Y02D 10/00 (2018.01)] | 20 Claims |
1. A system on chip (SoC) comprising:
a first master;
a second master;
an I2C interface configured to provide communication between an external device and the first master and/or provide communication between the external device and the second master; and
a multi-master controller configured to,
generate a plurality of operation codes corresponding to a request received from one of the first master and the second master,
set a control register based on first operation codes among the plurality of operation codes,
program data to the I2C interface based on second operation codes among the plurality of operation codes and the setting result,
determine whether the programming is completed based on third operation codes among the plurality of operation codes, and
send an interrupt to one of the first master and the second master based on a completion result of the programming.
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