CPC G02F 1/13338 (2013.01) [G06F 3/0412 (2013.01); G06F 2203/04103 (2013.01)] | 7 Claims |
1. An in-cell touch panel comprising a display portion, the display portion comprising:
a transistor;
a liquid crystal element comprising a first pixel electrode which is electrically connected to one of a source electrode and a drain electrode of the transistor;
a second pixel electrode adjacent to the first pixel electrode;
a first signal line electrically connected to the other of the source electrode and the drain electrode of the transistor;
a second signal line adjacent to the first signal line;
a scan line electrically connected to a gate electrode of the transistor; and
a touch sensor,
wherein the transistor comprises:
a semiconductor layer comprising a channel formation region;
a gate insulating layer over the semiconductor layer;
the gate electrode over the semiconductor layer; and
the source electrode and the drain electrode over the gate electrode with a first insulating layer therebetween,
wherein the liquid crystal element comprises:
the first pixel electrode; and
a common electrode,
wherein the common electrode is positioned below the first pixel electrode,
wherein the common electrode is positioned over the source electrode and the drain electrode with a second insulating layer therebetween,
wherein the common electrode is electrically connected to a first wiring,
wherein the touch sensor is electrically connected to a second wiring,
wherein the common electrode has a region overlapping with each of the first pixel electrode, the second pixel electrode, the first signal line, the second signal line, the first wiring, and the second wiring,
wherein, in a plan view, each of the first wiring and the second wiring has a region extending in a same direction as a direction in which the first signal line extends,
wherein each of the first wiring and the second wiring is positioned over the first insulating layer and below the second insulating layer,
wherein each of the first wiring and the second wiring comprises a same material as the first signal line,
wherein the scan line has a region overlapping with each of the first wiring, the second wiring, and the first signal line,
wherein the channel formation region of the transistor overlaps with the common electrode, and
wherein a light-blocking conductive film is positioned below the semiconductor layer and overlaps with the channel formation region of the transistor.
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