US 12,490,660 B2
Structures for three-terminal memory cells
Desmond Jia Jun Loy, Singapore (SG); Eng Huat Toh, Singapore (SG); and Shyue Seng Tan, Singapore (SG)
Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore (SG)
Filed by GlobalFoundries Singapore Pte. Ltd., Singapore (SG)
Filed on Dec. 13, 2022, as Appl. No. 18/065,041.
Prior Publication US 2024/0196626 A1, Jun. 13, 2024
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/24 (2023.02) [H10B 63/00 (2023.02); H10N 70/028 (2023.02); H10N 70/253 (2023.02); H10N 70/823 (2023.02); H10N 70/8833 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A memory structure comprising:
a source electrode having an upper surface;
a drain electrode having an upper surface;
a dielectric channel layer laterally between the source electrode and the drain electrode, the dielectric channel layer has a horizontal segment laterally between two vertical segments;
a hole generating layer on the dielectric channel layer, the hole generating layer has a horizontal segment laterally between two vertical segments, wherein the horizontal segment of the dielectric channel layer directly contacts the horizontal segment of the hole generating layer, and the two vertical segments of the dielectric channel layer are isolated from the two vertical segments of the hole generating layer by spacer layers; and
a control electrode on the hole generating layer, the control electrode has an upper surface, wherein the upper surface of the control electrode is substantially coplanar with the upper surface of the source electrode and the upper surface of the drain electrode.
 
9. A memory structure comprising:
a dielectric region;
a source electrode in the dielectric region;
a drain electrode in the dielectric region;
a dielectric channel layer in the dielectric region, the dielectric channel layer is laterally between the source electrode and the drain electrode;
a hole generating layer in the dielectric region, the hole generating layer is on the dielectric channel layer; and
a control electrode in the dielectric region, the control electrode has sides and a lower surface, wherein the hole generating layer is on the sides and the lower surface of the control electrode, and
wherein the dielectric channel layer has a horizontal segment laterally between two vertical segments, the hole generating layer has a horizontal segment laterally between two vertical segments, and the horizontal segment of the dielectric channel layer directly contacts the horizontal segment of the hole generating layer, the two vertical segments of the dielectric channel layer are isolated from the two vertical segments of the hole generating layer by spacer layers.