US 12,490,612 B2
Display substrate comprising signal lines and signal access pins and display apparatus
Donghui Tian, Beijing (CN); Fan He, Beijing (CN); Cong Fan, Beijing (CN); Rong Wang, Beijing (CN); Mengmeng Du, Beijing (CN); and Changlong Yuan, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 17/796,256
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 9, 2021, PCT No. PCT/CN2021/117423
§ 371(c)(1), (2) Date Jul. 28, 2022,
PCT Pub. No. WO2023/035178, PCT Pub. Date Mar. 16, 2023.
Prior Publication US 2024/0188361 A1, Jun. 6, 2024
Int. Cl. H10K 59/131 (2023.01); G09G 3/3266 (2016.01)
CPC H10K 59/1315 (2023.02) [G09G 3/3266 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01); G09G 2330/06 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate comprising a display region and a peripheral region located at a periphery of the display region, wherein the peripheral region comprises a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region which are communicated sequentially; the first peripheral region and the third peripheral region are located on two opposite sides of the display region along a first direction, and the second peripheral region and the fourth peripheral region are located on two opposite sides of the display region along a second direction, the first direction intersecting the second direction;
at least one first signal line located in the peripheral region, wherein the at least one first signal line comprises at least two sub-signal lines connected with each other; at least one sub-signal line of the at least one first signal line is located in the first peripheral region, and another at least one sub-signal line of the at least one first signal line is located in the third peripheral region; and
multiple signal access pins located in a signal access region, wherein the signal access region is located in the fourth peripheral region, or in the fourth peripheral region and the second peripheral region;
wherein each sub-signal line of the at least one first signal line extends to the signal access region and is connected with at least one signal access pin in the signal access region so as to be connected with a driver chip through the at least one signal access pin,
wherein the first peripheral region and the third peripheral region are provided with gate drive circuits connected with the at least one first signal line; and
a gate drive circuit comprises multiple drivers, the multiple drivers are arranged sequentially along a direction away from the display region, and at least one driver comprises multiple cascaded sub-drive circuits.