US 12,490,540 B2
Optical semiconductor array
Takehito Satoh, Kyoto (JP)
Assigned to Dexerials Corporation, Tochigi (JP)
Appl. No. 17/283,901
Filed by Kyoto Semiconductor Co., Ltd., Kyoto (JP)
PCT Filed Jun. 24, 2020, PCT No. PCT/JP2020/024809
§ 371(c)(1), (2) Date Mar. 9, 2023,
PCT Pub. No. WO2021/260841, PCT Pub. Date Dec. 30, 2021.
Prior Publication US 2023/0215895 A1, Jul. 6, 2023
Int. Cl. H10F 39/00 (2025.01); H10F 30/20 (2025.01)
CPC H10F 39/811 (2025.01) [H10F 30/20 (2025.01); H10F 39/024 (2025.01)] 1 Claim
OG exemplary drawing
 
1. An optical semiconductor array having a semiconductor substrate and a plurality of mesa-shaped optical semiconductor elements separated by grooves on the semiconductor substrate, wherein
each of the plurality of optical semiconductor elements comprises a semiconductor laminated part including a first semiconductor layer in contact with the semiconductor substrate,
a connecting hole formed at a portion separated from the groove in the semiconductor laminated part so as to extend from a surface of the semiconductor laminated part to the first semiconductor layer, and
a protective film having an insulating property covering the surface of the semiconductor laminated part and a cylindrical inner wall of the connecting hole; wherein
there are provided with an embedded protective film embedded in a whole of the groove so as to continue from the protective film, and a wiring for connecting, through the connecting hole of one of the adjacent optical semiconductor elements and a wiring connection portion formed through the protective film so as to expose a portion of the surface of the semiconductor laminated part of the other of the adjacent optical semiconductor elements, the first semiconductor layer of the one optical semiconductor element and a surface of the semiconductor laminated part of the other optical semiconductor element; wherein
a portion of the wiring is formed on a surface of the embedded protective film at a position passing the groove.