US 12,490,508 B2
Semiconductor device and method
Chun-Chieh Wang, Kaohsiung (TW); Yueh-Ching Pai, Taichung (TW); and Huai-Tei Yang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 8, 2022, as Appl. No. 17/835,169.
Application 17/835,169 is a division of application No. 16/895,035, filed on Jun. 8, 2020, granted, now 11,398,482.
Application 16/895,035 is a continuation of application No. 16/276,143, filed on Feb. 14, 2019, granted, now 10,679,995, issued on Jun. 9, 2020.
Claims priority of provisional application 62/712,504, filed on Jul. 31, 2018.
Prior Publication US 2022/0302116 A1, Sep. 22, 2022
Int. Cl. H10D 84/85 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/762 (2006.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H01L 21/027 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01)
CPC H10D 84/853 (2025.01) [H01L 21/0206 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/02532 (2013.01); H01L 21/30625 (2013.01); H01L 21/3065 (2013.01); H01L 21/76224 (2013.01); H10D 30/751 (2025.01); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/0172 (2025.01); H10D 84/0188 (2025.01); H10D 84/0191 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/859 (2025.01); H01L 21/0273 (2013.01); H01L 21/26513 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first fin on a semiconductor substrate, the first fin comprising a first semiconductor material on the semiconductor substrate and a second semiconductor material on the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material;
a shallow trench isolation region adjacent the first fin; and
a cap layer on the first fin, wherein the cap layer is made of a third semiconductor material, wherein the cap layer is in physical contact with side surfaces of the first semiconductor material, side surfaces of the second semiconductor material, and a top surface of the second semiconductor material, wherein interfaces between the side surfaces of the first semiconductor material and the third semiconductor material of the cap layer are disposed above a top surface of the shallow trench isolation region, and wherein the interfaces between the side surfaces of the first semiconductor material and the third semiconductor material of the cap layer extend lower than a topmost surface of the first semiconductor material in a cross-sectional view.