| CPC H10D 84/811 (2025.01) [H01L 23/345 (2013.01); H01L 23/373 (2013.01); H01L 23/5226 (2013.01); H02M 1/0012 (2021.05); H02M 1/0025 (2021.05); H02M 3/157 (2013.01); H10D 84/83 (2025.01)] | 20 Claims |

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1. A device structure comprising a voltage regulator circuit, wherein the voltage regulator circuit comprises:
a first semiconductor die including a pulse width modulation (PWM) circuit comprising a first set of field effect transistors located on a first semiconductor substrate and connected to a PWM voltage output node at which a pulsed voltage output is generated; and
a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies,
wherein:
a first end node of the series connection is connected to the PWM voltage output node;
a second end node of the series connection is connected to electrical ground;
each of the capacitor-switch assemblies comprises a respective series connection of a respective capacitor and a respective switch; and
each switch within the capacitor-switch assemblies is located within the first semiconductor die.
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