US 12,490,502 B2
Bipolar junction transistors and P-N junction diodes including stacked nano-semiconductor layers
Byounghak Hong, Albany, NY (US); Gunho Jo, Clifton Park, NY (US); Sooyoung Park, Clifton Park, NY (US); Hyoeun Park, Cohoes, NY (US); WookHyun Kwon, Hwaseong-si (KR); Jaehong Lee, Albany, NY (US); and Kang-ill Seo, Albany, NY (US)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 28, 2022, as Appl. No. 17/936,127.
Claims priority of provisional application 63/355,872, filed on Jun. 27, 2022.
Claims priority of provisional application 63/338,071, filed on May 4, 2022.
Prior Publication US 2023/0361112 A1, Nov. 9, 2023
Int. Cl. H10D 84/60 (2025.01); H10D 8/00 (2025.01); H10D 10/60 (2025.01); H10D 62/10 (2025.01)
CPC H10D 84/619 (2025.01) [H10D 8/422 (2025.01); H10D 10/60 (2025.01); H10D 62/121 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device including a bipolar junction transistor (BJT) and/or a P-N junction diode, the integrated circuit device comprising:
a first stack comprising:
first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type;
a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions, wherein the plurality of nano-semiconductor layers each have a second conductivity type different from the first conductivity type, and the first semiconductor region comprises a side surface facing the plurality of nano-semiconductor layers;
a vertical semiconductor layer having the second conductivity type, wherein the vertical semiconductor layer contacts the side surface of the first semiconductor region and the plurality of nano-semiconductor layers; and
a conductive contact that directly contacts the plurality of nano-semiconductor layers.