US 12,490,498 B2
Semiconductor device and manufacturing method thereof
Chun-Yen Lin, Hsinchu (TW); Wei-Cheng Lin, Taichung (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 1, 2023, as Appl. No. 18/327,787.
Prior Publication US 2024/0404886 A1, Dec. 5, 2024
Int. Cl. H10D 84/03 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 30/6735 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/83 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first channel structure through a first gate structure;
forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure;
before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and
after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer,
wherein the first surface and the second surface are opposite to each other, and
a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.