US 12,490,485 B2
Superjunction transistor device
Hans Weber, Bayerisch Gmain (DE); Björn Fischer, Munich (DE); Franz Hirler, Isen (DE); Matteo-Alessandro Kutschak, Ludmannsdorf (AT); and Andreas Riegler, Lichtpold (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Appl. No. 17/792,447
Filed by Infineon Technologies Austria AG, Villach (AT)
PCT Filed Jan. 19, 2021, PCT No. PCT/EP2021/051023
§ 371(c)(1), (2) Date Jul. 13, 2022,
PCT Pub. No. WO2021/148383, PCT Pub. Date Jul. 29, 2021.
Claims priority of application No. PCT/EP2020/051245 (WO), filed on Jan. 20, 2020; and application No. 20194876 (EP), filed on Sep. 7, 2020.
Prior Publication US 2023/0126534 A1, Apr. 27, 2023
Int. Cl. H10D 62/17 (2025.01); H03K 17/687 (2006.01); H10D 30/66 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01); H10D 84/00 (2025.01)
CPC H10D 62/307 (2025.01) [H03K 17/687 (2013.01); H10D 30/668 (2025.01); H10D 64/117 (2025.01); H10D 64/513 (2025.01); H10D 84/143 (2025.01); H10D 84/146 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A transistor device, comprising:
a semiconductor body;
a drift region in the semiconductor body;
a plurality of transistor cells;
a plurality of second mesa regions each arranged between two neighboring transistor cells and adjoining a first surface of the semiconductor body, wherein at least one of the plurality of second mesa regions comprises a section of the drift region that extends to the first surface;
a gate node; and
a source node;
wherein each of the plurality of transistor cells comprises:
a first trench electrode insulated from the semiconductor body by a first dielectric layer, and connected to the gate node or the source node;
a second trench electrode insulated from the semiconductor body by a second dielectric layer, and connected to the gate node, the source node or is floating;
a source region and a body region in a first mesa region between the first trench electrode and the second trench electrode; and
a compensation region,
wherein the compensation region adjoins the body region, the first dielectric, and the second dielectric, and forms a pn-junction with the drift region,
wherein the plurality of transistor cells comprises a transistor cell type in which the first trench electrode is connected to the source node and the second trench electrode is connected to the source node.