US 12,490,472 B2
Semiconductor device and semiconductor memory device
Ha Hoang, Mie (JP); Kazuhiro Matsuo, Mie (JP); and Kenichiro Toratani, Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 7, 2022, as Appl. No. 18/052,957.
Claims priority of application No. 2022-094570 (JP), filed on Jun. 10, 2022.
Prior Publication US 2023/0402548 A1, Dec. 14, 2023
Int. Cl. H01L 29/786 (2006.01); H10D 30/67 (2025.01)
CPC H10D 30/6755 (2025.01) [H10D 30/6757 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a cell capacitor and a transistor,
wherein the cell capacitor includes a first electrode coupled to a plate line and a second electrode coupled to the transistor, the transistor includes a first conductor, a second conductor, and a third conductor, which are aligned in a first direction and separated from each other;
a semiconductor including a metal oxide and extending in the first direction to be in contact with the first conductor and the third conductor;
a first insulator arranged between the semiconductor and the second conductor; and
an insulation region surrounded by the semiconductor and extending in the first direction to be in contact with the first conductor,
wherein the semiconductor includes a first portion and a second portion defined between the first portion and the insulation region, and
a concentration of a first element contained in the metal oxide of the semiconductor is higher in the second portion than in the first portion.