US 12,490,469 B2
Semiconductor device and method of fabricating the same
Ken-Ichi Goto, Hsinchu (TW); and Cheng-Yi Wu, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacuturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 5, 2023, as Appl. No. 18/164,600.
Claims priority of provisional application 63/419,307, filed on Oct. 25, 2022.
Prior Publication US 2024/0136441 A1, Apr. 25, 2024
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 62/40 (2025.01); H10D 62/84 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6741 (2025.01) [H01L 21/02488 (2013.01); H01L 21/02491 (2013.01); H01L 21/02502 (2013.01); H01L 21/02516 (2013.01); H01L 21/02521 (2013.01); H01L 21/02532 (2013.01); H01L 21/02565 (2013.01); H01L 21/02598 (2013.01); H01L 21/02609 (2013.01); H10D 30/031 (2025.01); H10D 30/6739 (2025.01); H10D 30/675 (2025.01); H10D 30/6755 (2025.01); H10D 62/405 (2025.01); H10D 86/423 (2025.01); H10D 86/425 (2025.01); H10D 86/431 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01); H10D 62/84 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first transistor disposed on the substrate, wherein the first transistor comprises:
a first channel layer, wherein a crystal orientation of the first channel layer is <100> or <110>;
a magnesium oxide layer located below the first channel layer and in contact with the first channel layer;
a first gate electrode located over the first channel layer;
a first gate dielectric located in between the first channel layer and the first gate electrode; and
first source/drain electrodes disposed on the first channel layer; and
a second transistor disposed on the substrate, wherein the second transistor comprises:
a second channel layer, wherein the second channel layer comprises indium-gallium-zinc-oxide (IGZO);
second source/drain electrodes disposed on the second channel layer;
a second gate electrode disposed on the second channel layer; and
a second gate dielectric located in between the second channel layer and the second gate electrode.