| CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
|
1. A method for tuning a threshold voltage of a transistor, comprising:
forming a channel layer over a substrate;
forming an interfacial layer over and surrounding the channel layer;
forming a gate dielectric layer over and surrounding the interfacial layer;
forming a dipole layer over and wrapping around the gate dielectric layer by performing a cyclic deposition etch process, wherein the dipole layer comprises dipole metal elements and has a substantially uniform thickness;
performing a thermal drive-in process to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface; and
removing the dipole layer.
|