US 12,490,453 B2
Heterostructure channel layer for semiconductor devices
Wen-Yi Lin, Tainan (TW); Shi-Sheng Hu, Tainan (TW); and Chao-Chi Chen, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 6, 2022, as Appl. No. 17/805,604.
Prior Publication US 2023/0395720 A1, Dec. 7, 2023
Int. Cl. H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/822 (2025.01)
CPC H10D 30/62 (2025.01) [H10D 30/751 (2025.01); H10D 62/822 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a fin structure on the substrate, wherein:
the fin structure comprises a channel layer comprising silicon and a bottom layer between the channel layer and the substrate;
the channel layer comprises first, second, and third portions on top of the bottom layer;
the second portion is between the first and third portions;
the first and third portions comprise a same material as the bottom layer; and
the second portion comprises a material different from the bottom layer; and
first and second source/drain structures on the bottom layer and adjacent to the channel layer, wherein the first source/drain structure is in contact with the first portion of the channel layer, and wherein the second source/drain structure is in contact with the third portion of the channel layer.