| CPC H10B 43/27 (2023.02) [H01L 21/0337 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10D 64/037 (2025.01); H01L 23/53295 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
an alternating layer stack, the alternating layer stack comprising conductive/dielectric layer pairs stacked in a first direction, each conductive/dielectric pair comprising a dielectric layer and a conductive layer;
a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer;
a channel structure extending through the alternating layer stack and the first insulating layer along the first direction, wherein the channel structure comprises:
an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer,
a functional layer on the epitaxial layer and extending along the first direction,
a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and
a filling structure covering a sidewall of the channel layer;
a channel column structure at a second end of the channel structure near the first insulating layer and in contact with the channel layer; and,
a top selective gate structure over the first insulating layer, covering end surfaces of the functional layer and the channel layer at the second end of the channel structure, and between neighboring channel column structures.
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