| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and
a second semiconductor structure on the first semiconductor structure, the second semiconductor structure comprising:
a second substrate having a first region and a second region;
a substrate insulating layer that extends through the second substrate;
a landing pad that extends through the substrate insulating layer;
gate electrodes spaced apart from each other and stacked on the first region in a first direction and extending with different lengths in a second direction on the second region, each of the gate electrodes including a gate pad region on the second region and having an exposed upper surface; and
a gate contact plug that extends through the gate pad region of at least one of the gate electrodes and extends into the landing pad in the first direction,
wherein the landing pad includes a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and wherein the landing pad includes a via portion that extends from the pad portion to the lower interconnection structure of the first semiconductor structure.
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