US 12,489,710 B2
Load balancing and networking policy performance by a packet processing pipeline
Anjali Singhai Jain, Portland, OR (US); Nupur Jain, Saratoga, CA (US); Elazar Cohen, Haifa (IL); John Andrew Fingerhut, Cary, NC (US); Neha Singh, Beaverton, OR (US); Vinoth Kumar Chandra Mohan, San Jose, CA (US); Alana Sweat, Hillsboro, OR (US); and Arunkumar Balakrishnan, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 1, 2022, as Appl. No. 17/958,349.
Claims priority of provisional application 63/283,135, filed on Nov. 24, 2021.
Prior Publication US 2023/0109396 A1, Apr. 6, 2023
Int. Cl. H04L 47/125 (2022.01); H04L 9/40 (2022.01); H04L 47/2483 (2022.01)
CPC H04L 47/125 (2013.01) [H04L 47/2483 (2013.01); H04L 63/0236 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a network interface device comprising packet processing circuitry, a host interface, a direct memory access (DMA) circuitry, and a network interface, wherein:
the packet processing circuitry is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause configuration of a second look-up-table accessible to the packet processing circuitry with the action for the identifier.