| CPC H04L 1/0042 (2013.01) [H04L 1/203 (2013.01)] | 30 Claims |

|
1. An apparatus for wireless communication at a wireless device, comprising:
one or more processors;
memory coupled with the one or more processors; and
instructions stored in the memory and executable by the one or more processors to cause the apparatus to:
obtain two or more sets of systematic bits and two or more sets of parity bits based on encoding a first set of information bits in parallel with at least one other set of information bits, wherein encoding the first set of information bits results in a first set of systematic bits of the two or more sets of systematic bits and a first set of parity bits of the two or more sets of parity bits;
obtain a second set of systematic bits and a second set of parity bits based on encoding a second set of information bits, in accordance with a concatenated encoding scheme, by using one or both of the first set of systematic bits and the first set of parity bits to encode the second set of information bits;
map at least the second set of systematic bits and the second set of parity bits to at least two layers of a constellation in accordance with a first priority of the first set of information bits and a second priority of the second set of information bits, wherein different sets of bits of the at least the second set of systematic bits and the second set of parity bits are mapped to different layers of the at least two layers of the constellation; and
transmit a signal associated with the second set of systematic bits and the second set of parity bits based at least in part on modulating the signal in accordance with the mapping.
|