US 12,489,549 B2
System-level techniques for error correction in chip-to-chip interfaces
Millind Mittal, Saratoga, CA (US); Krishnan Srinivasan, San Jose, CA (US); and Kenneth Ma, Cupertino, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Jul. 18, 2023, as Appl. No. 18/223,517.
Prior Publication US 2025/0030500 A1, Jan. 23, 2025
Int. Cl. H04L 49/9005 (2022.01); H04L 1/00 (2006.01)
CPC H04L 1/0041 (2013.01) [H04L 1/0025 (2013.01); H04L 49/9005 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving data message frames at a first die of a multi-die integrated circuit (IC) device, from a second die of the multi-die IC device;
detecting an error in a first one of the data message frames, by the first die;
transmitting a first control message frame, by the first die, requesting retransmission of the first data message frame;
transmitting second control message frames, by the first die, subsequent to the transmitting the first control message frame, indicating an idle operation at the first die;
receiving a third control message frame from the second die, by the first die, acknowledging the first control message frame;
halting the transmitting of the second control message frames based on the third control message frame;
transmitting a fourth control message frame, by the first die, indicating an end of a retransmission mode subsequent to the halting; and
receiving a retransmission of the first data message frame from the second die, by the first die, subsequent to the receiving the third control message frame.