| CPC H04B 7/06964 (2023.05) [H04L 5/0051 (2013.01); H04W 24/10 (2013.01); H04W 76/19 (2018.02)] | 18 Claims |

|
1. A processor, comprising:
memory storing instructions that, when executed, cause the processor to:
determine one or more beams to perform downlink communication from a base station;
receive, from the base station, a transmission configuration indicator (TCI) in an implicit indication, the TCI indicating:
a sounding reference signal (SRS), and
a first type of downlink reference signals based on the TCI;
determine that the first type of downlink reference signals are used in a same bandwidth part (BWP) as a control resource set (CORESET);
select the first type of downlink reference signals in order to perform beam failure detection and based at least in part on:
a lowest resource identifier (ID) of the first type of downlink reference signals;
the implicit indication;
a pathloss estimation for the SRS;
the determination that the first type of downlink reference signals are used in the same BWP as the CORESET; and
the SRS and the first type of downlink reference signals being indicated in the TCI;
perform signal quality measurements for the one or more beams using the first type of downlink reference signals; and
determine beam failure of at least one beam of the one or more beams based on said performing signal quality measurements.
|