| CPC H03M 13/095 (2013.01) [H03M 13/1111 (2013.01); H03M 13/13 (2013.01); H03M 13/2903 (2013.01); H04L 1/1819 (2013.01)] | 16 Claims |

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1. An apparatus for communication comprising:
one or more memories storing processor-executable code; and
one or more processors configured to execute the processor-executable code to cause the apparatus to:
decode a first set of bits from a first transmission, the first set of bits comprising a first subset of bits including first cyclic redundancy check (CRC) information, the first set of bits further comprising a second subset of bits including second CRC information, the first subset of bits being encoded on a first set of Polar code sub-channels associated with a first Polar code sub-channel quality and the second subset of bits being encoded on a second set of Polar code sub-channels associated with a second Polar code sub-channel quality that is lower than the first Polar code sub-channel quality; and
when a result of the decoding of the first set of bits is incorrect:
receive a second transmission that includes a second set of bits comprising the second subset of bits including the second CRC information from the first transmission;
decode the second set of bits; and
decode at least a portion of the first set of bits using the decoded second set of bits.
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