US 12,489,438 B2
Bias clamp circuit
Saiteja Burugupalli, Bangalore (IN); and Mahadevan Venkiteswaran, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 28, 2023, as Appl. No. 18/309,556.
Prior Publication US 2024/0364323 A1, Oct. 31, 2024
Int. Cl. H03K 17/16 (2006.01); G05F 3/20 (2006.01)
CPC H03K 17/161 (2013.01) [G05F 3/205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor having a source, a gate, and a drain, the drain of the first transistor coupled to a voltage supply terminal;
a second transistor having a source, a gate, and a drain, the gate of the second transistor coupled to the gate of the first transistor, and the source of the second transistor coupled to the source of the first transistor;
a third transistor having a first terminal and a bulk, the bulk of the third transistor coupled to the drain of the second transistor;
a fourth transistor having a first terminal and a bulk, the bulk of the fourth transistor coupled to the drain of the second transistor and the first terminal of the fourth transistor coupled to the first terminal of the third transistor; and
reference voltage supply coupled to the gates of the first and second transistors, wherein the reference voltage supply comprises:
a current source having first and second terminals;
a capacitor having a first terminal coupled to the second terminal of the current source and having a second terminal coupled to a ground terminal; and
a voltage clamp circuit coupled to the second terminal of the current source and the ground terminal.