US 12,489,432 B2
Integrated circuit device, method and system
Cheng-Yu Lin, Hsinchu (TW); Yung-Chen Chien, Hsinchu (TW); Jia-Hong Gao, Hsinchu (TW); Jerry Chang Jui Kao, Hsinchu (TW); and Hui-Zhong Zhuang, Hsinchu (TW)
Assigned to ASSIER CONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 2, 2024, as Appl. No. 18/624,868.
Application 18/624,868 is a continuation of application No. 17/825,704, filed on May 26, 2022, granted, now 11,979,158.
Claims priority of provisional application 63/268,403, filed on Feb. 23, 2022.
Prior Publication US 2024/0250671 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/00 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01); H03K 5/134 (2014.01)
CPC H03K 3/35625 (2013.01) [H03K 3/012 (2013.01); H03K 3/0372 (2013.01); H03K 3/356104 (2013.01); H03K 5/134 (2014.07)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a master latch circuit comprising a data output;
a slave latch circuit comprising a data input electrically coupled to the data output of the master latch circuit; and
a clock circuit electrically coupled to the master latch circuit and the slave latch circuit,
wherein the slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.