US 12,489,409 B2
Power amplifier
Kazuya Yamamoto, Tokyo (JP); and Satoshi Suzuki, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Appl. No. 18/249,197
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
PCT Filed Mar. 3, 2021, PCT No. PCT/JP2021/008271
§ 371(c)(1), (2) Date Apr. 14, 2023,
PCT Pub. No. WO2022/185459, PCT Pub. Date Sep. 9, 2022.
Prior Publication US 2024/0030879 A1, Jan. 25, 2024
Int. Cl. H03F 1/07 (2006.01); H03F 1/02 (2006.01); H03F 1/08 (2006.01); H03F 1/30 (2006.01); H03F 3/24 (2006.01)
CPC H03F 3/245 (2013.01) [H03F 1/0216 (2013.01); H03F 1/086 (2013.01); H03F 1/301 (2013.01); H03F 2200/451 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A power amplifier comprising:
a main transistor configured to amplify an input signal input from a gate terminal and output the amplified input signal from a drain terminal and having such characteristics of a drain current delay that, if a state of the input signal is switched from an ON state to an OFF state, after a drain current becomes lower than a reference value before the input signal is put into the ON state, the drain current returns to the reference value;
a replica transistor having the same characteristics of the drain current delay as the characteristics of the drain current delay of the main transistor, a temperature of the replica transistor changing in accordance with a temperature of the main transistor, and an envelope signal of the input signal being input to a gate terminal of the replica transistor;
an extraction circuit configured to extract a delay component due to the drain current delay from an output voltage of the replica transistor;
an adder configured to add the delay component to a gate bias voltage to be applied to the main transistor so as to cancel out the drain current delay of the main transistor; and
a signal generation circuit configured to generate the envelope signal from the input signal,
wherein the signal generation circuit is either a circuit including a directional coupler configured to branch the input signal, and an envelope detector configured to detect an envelope of the signal branched by the directional coupler, or a circuit formed with a second low pass filter.