US 12,489,319 B2
Wireless charging with hybrid sin/square reconfigurable RF waveform
Stephen Ellwood, Graz (AT); and Lukas Niederwieser, Graz (AT)
Assigned to Renesas Design Austria GmbH, Graz (AT)
Filed by Renesas Design Austria GmbH, Graz (AT)
Filed on Sep. 3, 2024, as Appl. No. 18/823,127.
Claims priority of application No. 23204398 (EP), filed on Oct. 18, 2023.
Prior Publication US 2025/0132606 A1, Apr. 24, 2025
Int. Cl. H02J 50/20 (2016.01); H01Q 3/28 (2006.01); H02J 50/23 (2016.01); H02J 50/40 (2016.01); H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03F 3/217 (2006.01); H03F 3/72 (2006.01); H03M 1/66 (2006.01); H03M 1/76 (2006.01)
CPC H02J 50/23 (2016.02) [H01Q 3/28 (2013.01); H02J 50/402 (2020.01); H03F 1/02 (2013.01); H03F 2200/249 (2013.01); H03F 2200/451 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A digital power amplifier to drive an RFID antenna with an antenna signal of an output current, the digital power amplifier comprising:
an integrated circuit having a first transmission output pin and a second transmission output pin to provide an output signal;
an adaption circuit of discrete components connected to the first transmission output pin and the second transmission output pin to adapt the output signal and feed the substantial sinusoidal output current with a transmission resonance frequency to the RFID antenna;
a digital control section with a number of W wave-forming contacts to output a digital wave-forming bit combination with a clock frequency M-times the transmission resonance frequency; and
a number of 2*W driver blocks each connected with a first contact to one of the wave-forming contacts and a number of W of them connected with a second contact to the first transmission output pin and the other number of W of them connected with their second contact to the second transmission output pin, which driver blocks are built to provide charge increments for the substantial sinusoidal output current to the first and second transmission output pin,
wherein the digital control section comprises:
switching means built to steer a logic cell in each of the driver blocks to disable at least four of the 2*W driver blocks of the digital power amplifier from a contributing mode into a none-contributing mode, in which none-contributing mode the driver block does not contribute charge for an increment to the output current, to adjust the amplitude and/or the waveform of the output signal, wherein that the digital control section is built to reduce the output power of the antenna signal with the substantial sinusoidal output current by stepwise symmetrically disabling those of the 2*W driver blocks into the none-contributing mode that enable to cut-off the highest amplitude of the positive and the negative halfwaves of the substantial sinusoidal output current and with each step transform the waveform of the substantial sinusoidal output voltage into a more and more substantial square wave output voltage.