US 12,489,065 B2
Fabrication method of semiconductor structure
Chin-Shan Wang, Hsinchu (TW); and Shun-Yi Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 3, 2021, as Appl. No. 17/338,292.
Application 16/222,355 is a division of application No. 15/255,350, filed on Sep. 2, 2016, granted, now 10,157,856, issued on Dec. 18, 2018.
Application 17/338,292 is a continuation of application No. 16/222,355, filed on Dec. 17, 2018, granted, now 11,270,952.
Claims priority of provisional application 62/343,535, filed on May 31, 2016.
Prior Publication US 2021/0296257 A1, Sep. 23, 2021
Int. Cl. H01L 23/552 (2006.01); H01L 21/762 (2006.01); H01L 23/58 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/76224 (2013.01); H01L 23/585 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming parallel first and second dummy materials in an alternating manner on a substrate;
etching of the first and second dummy materials, using respective selective etches, to form a plurality of gaps;
filling a first gap of the plurality of gaps with a dielectric material; and
filling a second gap of the plurality of gaps with a conductive material, wherein the conductive material extends below a top surface of the substrate.