US 12,489,049 B2
Semiconductor device and manufacturing method thereof
Chia-Cheng Ho, Hsinchu (TW); Chun-Chieh Lu, Taipei (TW); and Chih-Sheng Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 14, 2022, as Appl. No. 17/575,660.
Application 17/575,660 is a continuation of application No. 16/571,214, filed on Sep. 16, 2019, granted, now 11,227,828.
Prior Publication US 2022/0139822 A1, May 5, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H10D 1/68 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01)
CPC H01L 23/5223 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H10D 1/696 (2025.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor fin;
a gate structure disposed across the semiconductor fin;
a capacitor structure disposed on and in physical contact with the gate structure, wherein the capacitor structure comprises a ferroelectric layer, and a vertical projection of the capacitor structure lands on the semiconductor fin;
a conductive contact disposed on the capacitor structure, wherein the conductive contact is a single-layered structure;
a hard mask layer laterally surrounding the conductive contact, wherein the conductive contact protrudes from a top surface of the hard mask layer, and the conductive contact is in physical contact with the hard mask layer; and
a pair of spacers laterally surrounding the gate structure and the hard mask layer.