US 12,489,025 B2
Enhanced semiconductor structures and manufacturing methods thereof
Kai Cheng, Jiangsu (CN)
Assigned to ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
Appl. No. 17/628,534
Filed by ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
PCT Filed Sep. 10, 2020, PCT No. PCT/CN2020/114581
§ 371(c)(1), (2) Date Jan. 19, 2022,
PCT Pub. No. WO2022/052001, PCT Pub. Date Mar. 17, 2022.
Prior Publication US 2022/0359334 A1, Nov. 10, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 23/29 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H01L 23/3192 (2013.01) [H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A method of manufacturing an enhanced semiconductor structure, comprising:
forming a heterojunction structure, a cap layer, a first passivation layer and a second passivation layer sequentially on a semiconductor substrate;
forming a trench penetrating through the first passivation layer and the second passivation layer, wherein a part of the second passivation layer is removed by dry etching, the first passivation layer is used as an etching stop layer during the dry etching, a part of the first passivation layer is removed by wet etching, and the cap layer is used to protect the heterojunction structure during the wet etching;
forming a P-type semiconductor layer penetrating through the first passivation layer and the second passivation layer on an inner wall of the trench; and
forming an N-type ion heavily doped layer on the P-type semiconductor layer, wherein the N-type ion heavily doped layer penetrates through the second passivation layer and part of the first passivation layer;
wherein a thickness of the P-type semiconductor layer is less than a thickness of the first passivation layer.