US 12,489,021 B1
Determining a density of through-silicon vias in integrated circuits
I-Jye Lin, New Taipei (TW); and Gary K. Yeap, Fremont, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Oct. 19, 2022, as Appl. No. 18/047,977.
Claims priority of provisional application 63/262,957, filed on Oct. 22, 2021.
Int. Cl. H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H10D 88/00 (2025.01)
CPC H01L 22/12 (2013.01) [H01L 23/481 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H10D 88/00 (2025.01); H01L 2224/16245 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of determining a density of through-silicon vias (TSVs) for a die in a three-dimensional (3D) stacked die, comprising:
obtaining first power consumption information associated with a first die of the 3D stacked die;
obtaining second power consumption information associated with a second die of the 3D stacked die;
identifying, on the first die, an area associated with the second die, the identified area overlapping an area associated with the first die; and
determining a density of TSVs for the identified area based at least on the first power consumption information and the second power consumption information.