US 12,488,857 B2
Static random access memory (SRAM) fault correction
Darshan Kumar Nandanwar, Bangalore (IN); Kartik Gunvantbhai Desai, Savarkundla (IN); and Raghava Rao M V, Bangalore (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 13, 2023, as Appl. No. 18/466,110.
Prior Publication US 2025/0087295 A1, Mar. 13, 2025
Int. Cl. G11C 29/00 (2006.01); G11C 7/10 (2006.01)
CPC G11C 29/76 (2013.01) [G11C 7/1012 (2013.01); G11C 29/785 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory controller coupled to a memory module through a first channel and configured to store data in and access data stored in the memory module through the first channel, and configured to perform operations comprising:
receiving, from a host device, data to be stored in a memory of the memory module;
determining a row in the memory at which the data will be stored;
determining, based on the row, an address associated with the row, wherein the address indicates one bit location in the row at which data will not be stored; and
storing the data at the row in accordance with the address by adjusting a shift position of a multiplexer for storing the data at the row to bypass the one bit location based on the determined address, wherein the data is not stored at the one bit location.