US 12,488,851 B2
Content addressable memory apparatus, content addressable memory circuit and memory self-test method thereof
I-Hao Chiang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Mar. 5, 2024, as Appl. No. 18/595,469.
Claims priority of application No. 112110021 (TW), filed on Mar. 17, 2023.
Prior Publication US 2024/0312548 A1, Sep. 19, 2024
Int. Cl. G11C 29/36 (2006.01); G11C 29/20 (2006.01)
CPC G11C 29/36 (2013.01) [G11C 29/20 (2013.01); G11C 2029/3602 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A content addressable memory circuit, comprising:
a memory circuit configured to receive search data and an address signal so as to perform search operation and to generate a plurality of actual match signals corresponding to a plurality of the match lines, wherein a signal of a corresponding match line of the match lines is at a first state when the search data matches stored data related to the corresponding match line, and is at a second state when the search data does not match the stored data, and the signal of the corresponding match line is one of the actual match signals;
an internal test pattern generation circuit configured to receive a plurality of self-test driving signals to generate a plurality of expected match signals, wherein the internal test pattern generation circuit comprises a plurality of shift registers electrically coupled in series and has an amount equaling to an amount of the match lines, the shift registers are configured to receive an input signal comprised by the self-test driving signals and transmit the input signal one-by-one according to a clock signal comprised by the self-test driving signals and each of the shift registers is further configured to receive a reset signal comprised by the self-test driving signals to generate one of the expected match signals according to the transmitted input signal and the reset signal; and
an internal comparison circuit configured to receive and compare the actual match signals and the expected match signals to generate a plurality of match comparison results.